1. Field The Invention
This invention relates to data line interfaces, specifically to an interface providing parallel to serial conversion between a time division multiplexing bus and a data terminal interface.
2. Prior Art
In many modern data terminals, data is transmitted as units of information called bits. The data is transmitted at speeds such as 110, 300, 600, 1200 2400, 4800, 9600 and 19,200 bits per second. In these data terminals, characters are transmitted one at a time, i.e. asynchronously. Thus, these devices are called asynchronous machines. To be received in the proper sequence, each character must carry its own synchronization information.
There are many devices in the prior art that provide the synchronization information in the start-stop bits technique. Such devices transmit a variety of character sizes ranging from 5 to 8 bits of data, plus two to three bits for the start-stop function. The majority of these devices in the United States have a standardized 10-bit character consisting of a start bit (by convention, a logical 0) transmitted before each data word, (which is usually 8 data bits) and a stop bit after the end of the word (by convention, a logical 1). An asynchronous serial data receiver samples the data at a high rate to detect a start bit, calculates the start bit's center point, and activates its own clock at the nominal bit transmission rate to predict the center point of the successive data bits within each bit clock cycle. The bit signals are optimally sampled at their center points where they are most immune to noise interference. The receiver samples for the number of data bits expected in the data word, then samples for the stop bit at which time it turns off its clock bit. The source timing information is easily recovered from the start and stop bits.
It is much simpler to multiplex these devices character by character rather than bit by bit, particularly when the terminal to be multiplexed has different character sizes. For this reason, character interleaved time division multiplexers (hereinafter refer to as "TDM") have been widely adopted for these lower speed applications. Since individual characters may be sent out at a higher rate than received from the transmitter, the multiplexer must be able to buffer at least one character from the transmitter connected to it.
Generally, the data is received in a serial format which is converted to parallel format prior to input into the buffer. The timing information, start and stop bits are generally dropped from the character before buffering and the data is left as untimed data words in the memory buffer. The only information about the source timing is determined by how often the buffer is overwritten by the parallel bus with a new data word. Before the data is received by its destination circuit, it is normally converted back to serial data. If the source transmitter operates continuously at a slightly faster clock rate than the buffer during the parallel to serial conversion, data words will back up in the buffer. The buffer, however large, will eventually overflow and data words will be lost.
The reconversion of parallel to serial data is done by a clock derived from a TDM. This means that the maximum number of characters can be transmitted to the destination is fixed by this clock rate. Thus, there will be no overflow or lost word problems provided that the source of data has a clock rate slower than the clock in the TDM. However, if the clock of the data source is faster, then characters will be coming into the TDM faster than they can be transmitted to the destination.
In many prior art methods, the overflow problem is solved by running the clock for the parallel to serial conversion slightly faster than the nominal bit rate of the source clock. This guarantees that data overflow will not occur. However, these methods succeed in shortening every bit and thus, the system will suffer a loss in the error rate performance regardless of the character rate.
Therefore it is an object of this invention to provide a method and apparatus to regulate the rate of an asynchronous serial data transmission without causing data words to be lost.
It is another object of this invention to provide a method and apparatus to resynchronize a receiver so that it can tolerate a slightly faster than normal data reception.
These and other objects and advantages of the present invention will become apparent to those skilled in the art to which the invention pertains from the following detailed description when read in conjunction with the appended drawings. cl SUMMARY OF THE INVENTION
This invention is a data line interface providing a parallel to serial conversion technique for selectively increasing serial data transmission rates. The data line interface receives a 16-bit data word or signal from a TDM bus and transmits it serially to one of a plurality of data terminal interfaces called DTI's depending on which one is selected. The invention utilizes a double buffer receiver circuit to determine when to speed up the destination transmission clock. The system is comprised of a serial receiver receiving data at a source clock rate. The received data comprises a plurality of characters which have a start bit, followed by plurality of data bits and then one or more stop bits. The received data is converted to parallel format for transmission onto a parallel data TDM data bus at a rate controlled by a second clock. The data bus is coupled to a first buffer memory which is used to store data from the bus. The first buffer is coupled to a second buffer memory from which data is read by a bit transmitter to be transmitted through an output latch in serial format to a specified destination. The first and second buffers are coupled to a memory manager which controls when the data is transferred from the first buffer to the second buffer. The asynchronous data line interface looks at the value of each of the bits in the data word by sampling the center of each bit. However, during the stop bit, it will not look at the value after sampling the center. Thus, during the time that would have been devoted to the last half of the stop bit, a new start bit may be accepted, allowing the speed up of data to occur.